La-e801p Rev 2.0 Schematic |work| [ Exclusive – 2025 ]

| Section | Key ICs / Rails | Typical Voltages | | :--- | :--- | :--- | | | PQ30, PQ31 (MOSFETs), PU2 (BQ24735) | 19V → 19V_CHG | | System Rails | +3VALWP, +5VALWP (PU5 – TPS51225) | 3.3V, 5V always | | CPU Core | PU8, PU9 (NCP6132 or ISL95833) | Vcore: 0.8–1.2V | | PCH (Chipset) | +1.05V, +1.5V, +1.8V | Various LDOs | | RAM | +1.35V (DDR3L) or +1.5V | From PU6 | | EC (KBC) | MEC16 or MEC14xx | 3.3V, 3.3V_AUX |

The LA-E801P is built around the Intel processor series (7th Gen). Because this is a 2-in-1 convertible, the board is designed to handle frequent shifts in orientation, meaning the hinge and sensor connectors are critical points of failure often documented in the schematic. Key Components: CPU: Intel Core i3/i5/i7 (Soldered BGA). RAM: LPDDR3 (On-board, typically non-upgradable). la-e801p rev 2.0 schematic

: 30-pin or 40-pin eDP (embedded DisplayPort) connector supporting Full HD (1920x1080) touch panels. | Section | Key ICs / Rails |

A: Only as a very rough reference. Compal often moves pull-up resistors, changes component numbering (e.g., PU10 in Rev 1.0 becomes PU8 in Rev 2.0), and alters BOM. You risk shorting your board if you replace parts based on Rev 1.0. RAM: LPDDR3 (On-board, typically non-upgradable)

Repairing these boards requires more than just a soldering iron; it requires an understanding of the power sequence and signal flow. 1. Board Overview and Architecture