If you specifically require a (Gate Level) for educational purposes, you would instantiate a grid of full_adder modules, passing the carry from one to the next. This is rarely done in production code because it prevents the synthesis tool from using the chip's built-in DSP multipliers, resulting in a slower and larger circuit.
View waveforms: gtkwave dump.vcd (if a VCD file is generated by the testbench). 8bit multiplier verilog code github
The simplest way to write a multiplier is to let the synthesis tool (like Vivado or Quartus) decide the hardware. This is highly portable and usually results in an optimized DSP slice implementation on FPGAs. If you specifically require a (Gate Level) for
A7 A6 A5 A4 A3 A2 A1 A0 (8 bits) × B7 B6 B5 B4 B3 B2 B1 B0 (8 bits) --------------------------- A×B0 (shifted 0) → 8 bits A×B1 (shifted 1) → 9 bits (with overflow) A×B2 (shifted 2) → 10 bits ... A×B7 (shifted 7) → 15 bits --------------------------- Sum of all → 16-bit product The simplest way to write a multiplier is
Pipelining possible; fully custom. Cons: Higher LUT usage for large bit-widths (though 8-bit is small).
module multiplier_8bit( input [7:0] A, input [7:0] B, output [15:0] P );
// --------------------------------------------------------- // Step 1: Generate Partial Products (The AND gate grid) // --------------------------------------------------------- genvar i, j;